Recently, in the high speed transmission system, because of the usage of high performance forward error correcting technique such as low density parity code (LDPC), therefore transmission efficiency can be greatly enhanced. For LDPC (which will be referred to as LPDC decoder below), the decoding of the belief-propagation algorithm is used and is accomplished by interchanging and updating information between bit nodes and check nodes; however, the need of the nonlinear operation in updating the information of the check nodes will increase the hardware complexity and the cost. Hence, based on the economic consideration, usually a method with lower hardware complexity is used to substitute the higher complexity one. A well known method is the min-sum algorithm which is appropriate for the transmission environment with a higher SNR (signal-to-noise ratio). However, if the SNR is relatively low, then the approximation error will appear to be larger, which, in turn, will result in the reduction of the efficiency of error correction.
FIG. 1 shows an LPDC decoder diagram. The belief-propagation algorithm used in a LPDC decoder consists of continuously information exchanges between checking nodes and bit nodes. FIG. 2 shows a circuit block diagram of the checking node of the decoding device according to the prior art. The means for min-sum operation consists of a sorter 11 and an output selector 13, in which the sorter 11, after sorting the input values X1˜Xn from the bit nodes, outputs the two minimum values m1 and m2; and directly output the results r1˜rn via the output selector 13 without the provision of any compensation effect. Such an uncompensated configuration usually results in the reduction of the decoding performance. Additionally, although usually prior art techniques use a fixed constant to serve as a compensation term for the modification of the min-sum algorithm, it is still not enough for the provision of precise compensation effect.